1. Field of the Invention
This invention relates to circuits for filtering AC signals and to integrated circuits such as analog data separators and phase-locked loops containing active filters.
2. Description of Related Art
A variety of applications use filter circuits to remove unwanted frequency components from AC signals. One such application is a data separator containing a loop filter in a phase-locked loop. A data separator in a disk drive generates a data signal and a read clock signal from encoded pulses that a read head generates when reading a track on a disk. FIG. 1 illustrates the functional blocks in an exemplary data separator 100 which is a DP8473 available from National Semiconductor Corp. "The Floppy Disk Data Separator Design Guide for the DP8473," Application Note 505 describes the DP8473 data separator and is incorporated by reference herein in its entirety.
Data separator 100 contains a primary phase-locked loop 110 which generates a signal RCLK that is phase-locked to clock pulses in a signal Read.sub.-- Data.sub.-- In. Signal Read.sub.-- Data.sub.-- In typically contains clock pulses and data pulses that a read head generates while following a track, and the clock and data pulses have timing according to an encoding technique, typically frequency modulation (FM) or modified frequency modulation (MFM). A signal ENABLE to a phase comparator 112 indicates which of the pulses passing through a multiplexer 130 are clock pulses. Phase comparator 112 compares an edge of each clock pulse to a corresponding edge in signal RCLK and generates pump up and pump down signals which cause a charge pump 114 to either pump up (increase) a voltage VCNTL or pump down (decrease) the voltage VCNTL.
Voltage VCNTL is applied through a node 115 to a voltage controlled oscillator (VCO) 116 so that VCO 116 and a programmable divider 118 generate signal RCLK at a frequency that follows voltage VCNTL. A filter 120 removes high frequency components from voltage VCNTL to reduce jitter in signal RCLK and increase the ability of data separator 100 to accurately identify data. Filter 120 contains a capacitor 121 coupled between node 115 and ground and a capacitor 122 and a resistor 123 coupled in series between node 115 and ground. The filter response (V/I).sub.s of filter 120 is approximately equal to EQU (1+S*R1*C1)/[S*(C1+C2)*{1+S*R1*C1*C2/(C1+C2)}]
where S is the angular frequency of a voltage component applied to filter 120; R1 is the resistance of resistor 123; and C1 and C2 are the capacitances of capacitors 121 and 122.
Values R1, C1, and C2 are selected for the data rate (i.e. the frequency of the read clock signal). In an exemplary embodiment, capacitors 121 and 122 have respective capacitance of 1265 pF and 63 pF; and resistor 123 is a variable resistor having selectable resistances including 36.64 K.OMEGA., 18.1 K.OMEGA., and 8.58 K.OMEGA. corresponding to data rates of 250 KHz, 500 KHz, and 1000 KHz respectively. Filter 120 can be formed as part of an integrated circuit containing data separator 100. However, the total capacitance of filter 120 (about 1330 pF in the exemplary embodiment) requires a relatively large area (about 1.4 to 1.9 kmil.sup.2 drawn at 1 .mu.m design rules).